Digital computer with accumulator sign bit indexing

ABSTRACT

In lieu of a separate indexing register, the sign bit of the accumulator may be made to function as a single bit index register to effectuate address modification. In a machine so organized the instructions have a reserved bit position which gives the programmer the option of selecting modified or unmodified addressing. Because of the versatility of this type of instruction, only a few instructions are required to in-line program a variety of normally iterate routines.

United States Patent 1 Cavin et al. [4 1 June 5, 1973 [s41 DIGITALCOMPUTER WITH 3,111,648 ll/l963 Marsh et al ..340/|72.s

ACCUMULATOR SIGN BIT INDEXING OTHER PUBLICATIONS [76] Inventors: DoyleK. Cavin, 945 Verona Drive,

p n Robert Trousdak, IBM 7094 Data Processing System Reference Manual,13722 Rushmore Lane, Santa Ana, 10/21/55, A22-6703. P both of Calif. P Irimary Examiner-Pau J. Henon [22} 1971 Assistant Examiner-Mark EdwardNusbaum [2]] App], No; 114,902 Attorney-John A. Duffy and Bruce D.Jimerson Related U.S. Application Data 57 ABSTRACT cc'mimlamn'in-pan 0fC No. 790,735, Jan- 3. In lieu of a separate indexing register, the signbit of abandoned" the accumulator may be made to function as a singlebit index register to effectuate address modification. [2?] In a machineso organized the instructions have a 235/{57 reserved bit position whichgives the programmer the l e o are option of selecting modified orunmodified addressing. [56] References Cited Because oi: the versatilityof this typeofunstructnon, only a few instructmns are required to m-lmeprogram UNHED STATES p a variety of normally iterate routines.

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8 FREE MfMO/F/ 2% (OPE MEMORY 512-9 8/7 WGQDS/HW DIGITAL COMPUTER WITHACCUMULATOR SIGN BIT INDEXING BACKGROUND OF THE INVENTION Thisapplication is a Continuation-in-Part of an earlier filed copendingapplication Ser. No. 790,735, now abandoned, filed Jan. 13, 1969.

The utilization of special and general purpose digital computers forproblem solving is well-known in the art. Typically, such decisionmaking machines are designed to execute a variety of sequentialinstructions upon a quantity of input data and generate therefrom thedesired results whether they be mathematical answers, a series ofoperations for algorithm solutions, or merely the outputting ofparticularly specified stored data. The actual number of availableinstructions which a given machine is capable of executing will ofcourse depend upon the complexity of the machine. In a large generalpurpose computer, the instruction set may comprise hundreds ofinstructions, whereas a small special purpose machine may only utilize afew basic instructions which can be combined in various ways to performmore complicated functions. One disadvantage of the small machine havinga very limited set of instructions is that a number of basicinstructions must be written in the program to perform even very simplearithmetic operations. Thus, in a simple machine having an instructionset consisting only of add, shift, and output, a multiplicationoperation would require the programmet to separately command each of therepetitive additions with a consequent consumption of a great amount ofman and machine time. On the other hand, the more sophisticated andlengthy the instruction set, the more complex the machine. What isactually desired is a machine organization which is responsive to aninstruction set consisting of a few very powerful basic instructionswhich may be efficiently combined to enable simple inline programming ofnumerous standard routines which normally require complicated iterativeprogram loops. In some of the larger machines this operation isaccomplished by external address modification via individuallyaccessable auxilliary index registers. This same function may beconveniently accomplished in even relatively small computers inaccordance with the teachings of the present invention wherein, in lieuof separate indexing registers the machine is structured to have thecapability of being able to respond to and directly operate uponinformation contained in the standard computational registers. Inparticular, the sign bit of a standard accumulator may be utilized as asingle bit index register to control alternate choice operations.

Accordingly, it is an object of the present invention to provide acomputer having an instruction set comprising a small number of veryversatile instructions.

It is another object of the invention to provide a computing machinehaving an internal means for data and address modification which is notdependent upon separate indexing registers.

It is a further object of the invention to provide a computer whichutilizes the accumulator sign bit as an index register.

Other objects and advantages of the present invention will becomeobvious from the detailed description of a preferred embodiment givenhereinbelow.

SUMMARY OF THE INVENTION The accumulator sign-bit indexing computerdescribed herein comprises an arrangement for organizing a generalpurpose machine which will utilize the information provided by the signof the accumulator contents in a variety of alternate choice operations.In essence the accumulator sign bit functions as a single bit indexregister to facilitate address modification in ac- 0 cordance with thedictates of certain indexing instructions. Each such accumulatorindexing instruction has reserved a designated bit position for thepurpose of controlling which of two addresses will be accessed by theparticular instruction.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a generalpurpose digital computer.

FIG. 2 illustrates a typical instruction format.

FIG. 3 is a flow chart for performing the digital plotting of a straightline.

FIG. 4 is a flow chart for multiplying two binary numbers together.

FIG. 5 shows how a double length accumulator functions in amultiplication routine.

FIG. 6 shows the flow of the multiplication algorithm of four bit binarynumbers to multiply three by six.

FIG. 7a shows how the accumulator sign bit and least significant bit maybe utilized to effectuate a four way ump.

FIG. 7b is a table of the four possible combinations of sign bit andleast significant bit.

FIG. 8 shows in block diagram form the requisite blocks and flow pathsinvolved in carrying out a typical indexing operation.

DETAILED DESCRIPTION OF A PARTICULAR EMBODIMENT FIG. 1 shows a blockdiagram of a typical general purpose computer having the standardelements comprising an input/output means I, a memory 2, arithmeticcenter 3, and control unit 4. For the purposes of the present invention,the memory 2 may be of any type such as a random access core, thin film,MOS or serial accessed drum, disk or delay line. The computer may beorganized to have a fixed or variable word size of any length (number ofbits). The number system employed may be full binary with negativequantities expressed in one's or two's, complement notation, or a signand magnitude form may be employed using binary coded decimal or anyother system in which the sign of information representing a given dataword is represented by a particular bit at a fixed location in the word.The arithmetic center 3 comprises an accumulator 5 which may consist ofactual hardware (such as a set of flip flops or the like) or which mayoccupy some fixed or alterable location in the memory 2. The capacity ofthe accumulator 5 may be fixed or variable and may or may not be relatedto the word size of stored values in the memory 2. The logic means 8 inFIG. I is typically an AND" gate.

The instruction set defining the computational capability of thecomputer should include a standard "add" or subtract" instruction sothat the accumulator contents may be modified by the contents ofselected stored values in the memory to produce a resultant quantity inthe accumulator having a positive or negative sign. In addition, theinstruction set should include a standard load" instruction whereby thecontents of a particular address in the memory 2 may be placed in theaccumulator 5; an output instruction whereby the contents ofa particularlocation in the memory 2 or accumulator 5 may be transferred to anoutput device 9, such as a magnetic tape, typewriter, electronicplotter, etc.; a conditional jump instruction whereby the sign of aparticular memory address (or of the accumulator) is examined todetermine the address of the next instruction; an accumulator shiftinstruction; an input instruction, a load accumulator instruction, and astore instruction.

Although the application of the internal indexing and addressmodification features of the present invention are described in detailwith respect to a few of the above enumerated instructions, it will beunderstood that the instruction set may include numerous otherinstructions and that the basic concepts of the present invention (to bedescribed below) may also be combined therewith.

Adverting to FIG. 2, a typical standard instruction comprises a command(bits l-N) specifying some basic operation, e.g., ADD", "SUBTRACT",STORE", LOAD", 0UTPUT", "INPUT", etc., together with an operand address(bits N l to X) which points to a specific location in the memory whichcontains the operand to be used in the instruction. Where iterativeloops are to be programmed, it is convenient to be able to modify theaddress portion of the instruction. Thus, assume for example that it isdesired to form the sum of a long column of numbers which are located inconsecutive addresses of the computer memory from address 030 to 077. ITis thus possible to use the same add instruction for successiveadditions provided that the address of the ADD instruction is modifiedbefore each addition so as to add the contents of the next successiveaddress to the partial sum each time around. In prior art digitalcomputing devices, address modification is effectuated by an auxilliarymeans so that the operand actually accessed by the instruction can bevaried as a function of the contents of the auxilliary means.Conventionally, the auxilliary means employed is an independent indexregister, the contents of which is normally modified by a specialinstruction which is independent of the instructions which change theaccumulator contents. Hence, in the above example, an index register maybe loaded with the value of the first address and then incremented onecount each time an addition is made to access consecutive memoryaddresses.

An important feature of the present invention is the facility todirectly modify an address without resorting to special indexinginstructions and additional registers apart from the accumulator. Inessence, the sign bit of the accumulator 5 functions as a single bitindex register. In addition, the computer is organized to be responsiveto a set of instructions having a control bit I, for enabling theprogrammer to select unmodified or modified (indexed) addressing. Thus,if indexed addressing is selected, the operand address is taken to bethe direct value specified in the instruction when the accumulatorcontains a positive number (sign bit positive) whereas if the sign bitis negative the operand address is taken to be the direct value plus aknown increment (typically +1 or +2) which may vary depending upon thespecific instruction. This function is accomplished by the logic means 8as shown in FIG. I.

In order to illustrate the advantages of a digital computer soorganized, consider the following instruction set:

LDA( Y),0 Load accumulator with contents of location Y LDA( Y),l Loadaccumulator with the contents of location Y if the accumulator (A) ispresently positive or with the contents of Y I if A is presentlynegative.

ADD( Y),0 Add contents of location Y to contents of accumulator.

ADD(Y),1 Add contents of location Y if accumulator is positive orcontents of location Y I in accumulator is presently negative.

0UT( Y),0 Transfer the contents of location Y to an output device.

OUT(y),l Transfer the contents of location Y to an output device ifaccumulator is positive or contents of Y I if accumulator is presentlynegative.

DIJB( W) Decrement the contents of the memory cell immediately followingthat in which this instruction is stored. If the cell contents does notunderflow, jump back N instructions (i.e., take next instruction from alocation N memory cells prior to the location of the D118 instruction)With only these few selected instructions, a computer program may bewritten to perform, for example, a commonly used algorithm forapproximating a straight line by incremental plotting. Thus, assume thatthe X and Y directional components of the line are given as having aratio of A to B and that the line is to have a magnitude of C"increments. If the plotting device is responsively coupled to thecomputer as an output device so as to execute incremental movementsparallel to either the X or Y axis according to whether code X or code Yrespectively is transmitted to the output, the line may be plottedaccording to the flow chart shown in FIG. 3. The complete program may bewritten simply OUT(X),I

ADD(A),I

DIJB(2) where the constant code X and code Y are stored in twosuccessive locations so that the 0UT(X),I instruction will cause code Xto be selected if the accumulator is positive or code Y to be selectedif the accumulator is negative. Similarly, the constants A and B arestored in two successive locations so that either A is added to theaccumulator or B is subtracted from the accumulator depending upon theaccumulator sign with the ADD(A), l instruction. The count value C l isstored in the location immediately following the DUB instruction so thatit may be decremented once each recursion until underflow occurs.

The three-step routine described above for performing the commonstraight line algorithm is typical of the program simplicity whichresult when the computing machine is adapted to utilize the sign of theaccumulator contents to facilitate address modification. To furtherillustrate the versatility of utilizing the special index in combinationwith the information provided by the accumulator sign bit to effectuatealternate choice operation, consider the flow chart shown in FIG. 4 formultiplying two binary numbers together. In this application the signbit is employed as a value indicator for determining whether or not themultiplicand is added. Assume that the computer is arranged to have adouble length accumulator, as shown in FIG. 5, so that initially themultiplier may be placed in the left most bits (upper half) and thelower half may be set to zero. The sign bit of the accumulator is usedto determine whether or not the multiplicand is to be added to thepartial sum after each left shift of the accumulator. in essence, eachof the multiplier bits is successively examined as to sign and discardedby a left shift operationwhich also has the effect of left shifting thepartial sum for proper addition of the multiplicand (or zero) dependingupon the sign of the next multiplier digit. Thus, if the sign bit 1,addition of the multiplicand is performed, otherwise not. When a numberof shifts equal to the number of bits of the multiplier has beenperformed, the multiplication routine will be complete and the productwill be contained in the double length accumulator. By adding three moreinstructions, namely:

RSA Right Shift Accumulator LSA Left Shift Accumulator ADR(M),1 Addcontents of memory location (M) to right half of accumulator as indexedby sign of accumulator, a loop for implementing the algorithm using signbit indexing may be written as:

ADR(M),l

LSA

DIJB(2) RSA wherein M contains the value zero, M 1 contains themultiplicand and DIJB( 2) is followed by the number of bits of themultiplier. In FIG. 6 an example is given showing the various states ofthe accumulator in executing the multiplicantion of two four-bit numbersaccording to the dictates of the above loop. The multiplicand is takento be 3(0011) and the multiplier is taken to be 6(0110). initially, theupper half of the accumulator contains the multiplier (0] l0) and thelower half is coded with zeros. It will be seen that one right shift ofthe accumulator contents (step 10) is required to properly position theproduct 18 (00010010) in the accumulator following the last left shift(step 9).

As a further example of the potency of sign bit indexing, consider theapplication of the concept to a conditional jump instruction. in thestandard jump instruction, the computer is instructed to take the nextinstruction in sequence or, alternatively, to take the next instructionfrom some part of the memory other than the usual sequence. The decisionas to which course is to be followed will typically depend upon acomparison of stored values, e.g.,

Negative Jump If accumulator is negative, take next instruction fromaddress a. If accumulator is positive, continue in sequence.

Positive Jump lf accumulator is positive, take next instruction fromaddress a. If accumulator is negative, continue in sequence.

Zero Jump If accumulator is zero, take next instruction from address or;otherwise continue in sequence. As evidenced by each of the abovestandard instructions, the programmer has a choice between twolocations. With a sign bit indexing computer however, a four-way jump isavailable. Thus, assume that the jump instruction provides that a jumpis to be made to a new location ,6, if the contents of the accumulatoris odd. Accordingly, a jump instruction stored in location (a 1) willcause the next instruction (at) to be taken in sequence or,alternatively, the next instruction will be taken from cell ,8 dependingupon the state of the least significant bit of the accumulator asindicated in FIG. 7a. Now, if accumulator sign bit indexing is employed,and if the low order bit is odd, the address B will be indexed by one ifthe contents of the accumulator is negative, i.e., the next instructionwill be taken from mem ory cell [3 or 3+1 depending upon the algebraicsign of the contents of the accumulator. if, however, the contents ofthe accumulator is even, the next instruction will be taken from a ora+l depending upon the sign bit of the accumulator. The four possiblecombinations may therefore be summarized as shown in FIG. 7b.

FIG. 8 shows a block diagram illustrating the various flow paths in apreferred arrangement for practicing the invention. The memory 2 isdivided into eight pages. Each page corresponds to a word capacity of512 words. Each word in the memory is nine bits. A complete instructionword for the machine is 18 bits but only the first nine bits are storedin the nine bit instruction register 14. The last nine bits specify theaddress of the operand this information being stored in the next word inmemory. The first bit I, of the instruction register 14 indicateswhether or not the address of the operand is to be indexed. The secondbit is used to designate the page in the memory, i.e., the present pageor page one of the memory. The third bit is used for indirectaddressing. The remaining six bits of the instruction register specifythe command (i.e., add, subtract, multiply, etc.). The indexing featurerequires three cycles (two fetch and one execute cycle) which may bedescribed as follows:

During the first fetch cycle F, the memory address register is loaded(via line 33) with the address of the instruction to be executed. Theinstruction stored in this address is transferred to the memory bufferregister 22. These nine bits specify the command portion of theinstruction and are transferred during F, to the instruction register 14as indicated by the path 34.

The contents of the memory address register 21, are also augmented byone at the end of the F, cycle via the adder 23. This operation isindicated by the paths 35 and 36. At this time the memory addressregister will thus specify the address of the second portion of theinstruction.

During the F, cycle, the second part of the instruction (the operandaddress) is transferred to the memory buffer register 22 and then to theadder 23, as indicated by path 37. This address is then incremented byone via adder 23, if the index bit I, of the instruction register 14 istrue (i.e., indexing is commanded) and if the contents of theaccumulator is negative (sign bit 1). Logic means 8 is typically an"AND" gate whose output is true only if A, and I, are both true. Theresult of this addition is transferred from the adder to the memoryaddress register via path 36.

During the execute cycle E, the operand specified by the address storedin the memory address register 21 is transferred to the buffer register22 and then to the arithmetic unit (as indicated by 39) for execution inaccordance with the instruction command as decoded by the command decodelogic (path 40). The program counter 24 is then augmented by two countsand the next F cycle is commenced by storing the address of the firstportion of the next instruction in the memory address register 21.

The indexing feature may be used to perform almost any type of alternatechoice operation. Furthermore, the sign of the accumulator may be takento represent the sign of a number (as in the first example) or the valueof a selected bit (as in the second and third examples). As previouslymentioned, the indexing may be applied to numerous other instructionssuch as load, store, subtract, subtract outputs, inputs, etc. Incomputers containing indirect addressing capability (i.e., where theinstruction is used to specify not the address of the operand, butrather the location where the address of the operand may be found), theindexing feature of the present invention may be employed to provide analternative between different pointers of addresses of operands. In thisapplication, the operands of interest may be stored anywhere in thememory and the instruction is used to effectuate the choice between twoaddresses which specify the actual operand locations.

Although preferred embodiments of the present invention have been shownand described herein, it is understood that the invention is not limitedthereto, and that numerous changes and modifications may be made withoutdeparting from the spirit of the invention.

We claim:

I. A digital computer (comprising) having a control unit, a memory forstoring instructions having a command field and an operand addressfield, and an arithmetic unit including an accumulator wherein theimprovement comprises:

(an accumulator having) a particular bit position in said accumualatorfor representing the sign of information contained in said accumulator;

logic means for identifying the state of said sign bit;

instruction register means within said control unit responsive to thetransfer of an instruction from said memory for storing the instructioncurrently being executed;

arithmetic means within said arithmetic unit responsively connected tosaid logic means for modifying the operand address of the instructionwhich is stored in said instruction register means and is currentlybeing executed, based upon whether the state of said sign bit of saidaccumulator is a binary one or a binary zero.

2. In a digital computer (comprisingz) havinga memory for storinginstructions having a command field and an operand address field andhaving an arithmetic unit which includes an accumulator, the improvementwhich comprises:

(and accumulators having) a particular bit position in said accumulatorfor representing the sign of information contained in said accumulator;

instruction register means for storing the instruction currently beingexecuted;

control means responsive to unmodified instructions for executing theinstruction upon an operand specified by the address of the instructionirrespective of the state of said sign bit;

means for sensing the sign bit of said instruction register;

(control) arithmetic means responsively connected to said memory andresponsively connected to said means for sensing the sign bit modifiedinstructions, for altering the address where the operand of theinstruction being executed is stored based upon whether said sign bit isa binary one or a binary zero.

l k t l

1. A digital computer (comprising) having a control unit, a memory forstoring instructions having a command field and an operand addressfield, and an arithmetic unit including an accumulator wherein theimprovement comprises: (an accumulator having) a particular bit positionin said accumualator for representing the sign of information containedin said accumulator; logic means for identifying the state of said signbit; instruction register means within said control unit responsive tothe transfer of an instruction from said memory for storing theinstruction currently being executed; arithmetic means within saidarithmetic unit responsively connected to said logic means for modifyingthe operand address of the instruction which Is stored in saidinstruction register means and is currently being executed, based uponwhether the state of said sign bit of said accumulator is a binary oneor a binary zero.
 2. In a digital computer (comprising:) having a memoryfor storing instructions having a command field and an operand addressfield and having an arithmetic unit which includes an accumulator, theimprovement which comprises: (and accumulators having) a particular bitposition in said accumulator for representing the sign of informationcontained in said accumulator; instruction register means for storingthe instruction currently being executed; control means responsive tounmodified instructions for executing the instruction upon an operandspecified by the address of the instruction irrespective of the state ofsaid sign bit; means for sensing the sign bit of said instructionregister; (control) arithmetic means responsively connected to saidmemory and responsively connected to said means for sensing the sign bitmodified instructions, for altering the address where the operand of theinstruction being executed is stored based upon whether said sign bit isa binary one or a binary zero.